Extendible microprocessors have been developed which allow the user to add application-specific logic extensions to a base microprocessor design. This technique seeks to share the benefits of a standard microprocessor design and application-specific logic. By utilizing a standard microprocessor, a designer would seek to perform the majority of required functions by executing program code. The designer will benefit from the flexibility of this approach—the function of the design can be changed after hardware is produced by changing the program code. The designer will also benefit by having access to existing software infrastructure such as compilers, debuggers, operating systems and application code. By utilizing an application-specific logic design, a designer could gain the maximum performance for the application with the minimum logic area—however the function of the design will be fixed in hardware and no changes can be made once the hardware is produced.
The extendible microprocessor shares the benefits of these two approaches—special application-specific extension instructions, registers and interfaces are added to the design. As in the standard microprocessor case, the function of the design is still controlled by a software program, hence the function of the design can still be changed after hardware is produced; and software infrastructure designed for the base microprocessor can be used with extended variants of the processor. High performance can be obtained as key parts of the program are accelerated by adding the application-specific extension functions.
Some disadvantages of the previously described approaches still exist—in some cases software designed for the base microprocessor must be modified for use with an extended variant, this applies especially to operating systems (OS); once hardware is produced the function of the application-specific extensions cannot be changed, meaning that any changes to the function of the design must be achieved by changes to the program that sequences the base and extension operations.
The description herein of various advantages and disadvantages associated with known apparatus, methods, and materials is not intended to limit the scope of the invention to their exclusion. Indeed, various embodiments of the invention may include one or more of the known apparatus, methods, and materials without suffering from their disadvantages.
As background to the techniques discussed herein, the following references are incorporated herein by reference: U.S. Pat. No. 6,862,563 issued Mar. 1, 2005 entitled “Method And Apparatus For Managing The Configuration And Functionality Of A Semiconductor Design” (Hakewill et al.); U.S. Ser. No. 10/423,745 filed Apr. 25, 2003, entitled “Apparatus and Method for Managing Integrated Circuit Designs”; and U.S. Ser. No. 10/651,560 filed Aug. 29, 2003, entitled “Improved Computerized Extension Apparatus and Methods”, all assigned to the assignee of the present invention.